1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a gate electrode on a semiconductor substrate which reduces line resistance and formation of ohmic contacts.
2. Discussion of the Prior Art
Typically, to reduce gate resistance when forming a gate electrode on a semiconductor device, tungsten(W) having a specific resistance lower than WSi.sub.x by 1 order is deposited on polysilicon. The tungsten is then patterned to form a gate electrode. However, when tungsten reacts with polysilicon at a temperature of 600.degree. C. or greater, a silicide forms at the boundary between tungsten and polysilicon. Therefore, tungsten nitride WN.sub.x is often used as a diffusion barrier layer between the tungsten and polysilicon, thereby forming a gate electrode having a W/WN.sub.x /polysilicon structure.
Although WN.sub.x is commonly used as the diffusion barrier layer, TiN may also be used. When W is deposited on TiN by a sputtering method, the grain size of W is smaller than the W/Si structure. In this scenario, resistance increases by a factor of two or more in comparison to pure W. Furthermore, the TiN is oxidized during the selective oxidation of the polysilicon layer. For these reasons, WN.sub.x is commonly used as the diffusion barrier layer. This is disclosed by Y. Akasaka in the article, "Low-Resistivity Poly-Metal Gate Electrode Durable for High-Temperature Processing" (IEEE Trans. Electron Devices, Vol. 43, pp. 1864-1869, 1996), and by B. H. Lee in the article "In-situ Barrier Formation for High Reliable W/barrier/poly-Si Gate Using Denudation of WN.sub.x on Polycrystalline"(IEDM, 1998).
One method for forming a gate electrode on a semiconductor device will be described with reference to the accompanying drawings.
FIGS. 1A to 1E are cross-sectional views showing the steps of a related art method for forming a gate electrode on a semiconductor device.
As shown in FIG. 1A, field oxide layers 12 are formed in a semiconductor substrate 11 in which an active region and a field region are defined. Using thermal oxidation a gate oxide layer 13 is formed on a surface of the semiconductor substrate 11 at a thickness of about 65 .ANG..
As shown in FIG. 1B, an undoped polysilicon layer 14 is formed by a low pressure chemical vapor deposition (LPCVD) method on the entire surface of the semiconductor substrate 11 at a thickness of about 2000 .ANG.. N+ ions or P+ ions are then implanted into the polysilicon layer 14. When the N+ ions or P+ ions are implanted, As or P ions are implanted into a negative-channel metal oxide semiconductor (NMOS) region while B or BF.sub.2 ions are implanted into a positive-channel metal oxide semiconductor (PMOS) region using a photoresist as a mask.
Then an annealing process is performed in the polysilicon layer 14 for ten minutes and at a temperature of 800.degree. C. to activate the impurity ions.
As shown in FIG. 1C, the semiconductor substrate 11 is washed by HF solution and then WN.sub.x layer 15 is formed on the polysilicon layer 14 at a thickness of 50.about.100 .ANG.. A tungsten layer 16 is formed on the WN.sub.x , layer 15 at a thickness of about 1000 .ANG. and a first insulating layer 17 is deposited on the tungsten layer 16 at a thickness of about 2000 .ANG..
The WN.sub.x layer 15 is used as a diffusion barrier between the tungsten layer 16 and the polysilicon layer 14, and the first insulating layer 17 is used as a gate cap insulating layer later.
As shown in FIG. 1D, a photoresist(not shown) is deposited on the first insulating layer 17 and then patterned by exposure and developing processes to define a gate electrode region. The first insulating layer 17, the tungsten layer 16, the WN.sub.x layer 15, the polysilicon layer 14 and the gate oxide layer 13 are selectively removed using the patterned photoresist as a mask to form a gate electrode 18 having a structure consisting of a tungsten layer 16, a WN.sub.x layer 15 and a polysilicon layer 14.
As shown in FIG. 1E, selective oxidation is performed in the gate electrode 18 to partially form an oxide layer (not shown) at the sides of the gate electrode 18. Then a second insulating layer is formed on the entire surface of the semiconductor substrate 11. The second insulating layer is etched back to form second insulating layer sidewalls 19 on both sides of the gate electrode 18 and the first insulating layer 17.
However, the related art method for forming a gate electrode on a semiconductor device has several problems. When W/WN.sub.x is deposited on polysilicon, a W--Si--O--N layer forms at the boundary between tungsten and polysilicon during a later annealing process having a temperature of 800.degree. C. or more. Thus, boundary resistance between tungsten and polysilicon increases thereby slowing the operation of the semiconductor device.